Comments

Shendkar - You can collect the setup of tanner tools demo from me. (preferably during practical timing 5 to 7pm on Thursday)

List of Practicals

All the students must prepare a record of practicals in 100 Page notebook.
And write the experiments done in it.
Note : Give importance to doing the experimentation and then report.
1. Getting to know with the simulation Tools- such as Microcap, Microwind, Tanner Tools, Switcher CAD etc. (Week3-Dec 29, 2008 to Jan 3, 2009)
2. Simulation of simple schematics (consisting of R, L, C, Diode, Transistor)- (Week 4- Jan 5-10, 2009)
3. Simulation of Static CMOS gates and complex gates. such as 2 input EXOR, 4 to 1 multiplexer.
(note first perform the simulations for 2 input AND, OR, Inverter gates and Transmission gates.
(Week 5- Jan 12-17, 2009)
4. CMOS inverter Static characteristics for various values of Bn/Bp. Design of inverter for a specific threshold voltage and specific size. (week 6- Jan 19-24, 2009)
5. (for 29th Jan 2009) Simulate the dynamic behaviour of the CMOS Inverter.
Note : On 29th January, There is a open talk "MAZI SHODH YATRA " by Mr. Achyut Godbole, a renowned writer in Marathi and a successful IT professional at 6.00 PM at Shankarrao Chavan Sabhagrih, Near Guru Gobind Singhji Stadium. You may attend the same. It would be useful.
6. Dynamic behavior of CMOS inverter (rescheduled on 5th Feb 2009)
7. Layout design of various two input gates, complex logic such as sum and carry logic for full adder with equal and minimum rise and fall times.
8. Study of Layout versus Schematic



This list will be updated every Monday.

Syllabus

MEC603 VLSI DESIGN
Introduction to CMOS circuits, MOS Transistor, CMOS Logic The inverter, combination logic, The NAND and NOR Gates, Compound gates, Multiplexers, Memory Latches and Registers, Circuit and Systems representation and examples Behavioural, Structural and Physical representation
Review of MOS Transistor Theory nMOS and pMOS Enhancement transistor, Threshold voltage equations, Body effects, MOS device Design equations, Basic DC equations, second order effects, MOS Models, Complementary CMOS inverter DC Charac­teristics, Noise margin, Static load MOS Inverters, Differ­ential Inverter, the transmission gate, Tristate Inverter, BiCMOS Inverters, SPICE Model
CMOS Processing Technology Basic CMOS technology, n and p well processes, CMOS Process Enhancements, Layout design rules, Technology related CAD issues
Circuit Characterization and performance Estimation, Resist­ance and capacitance estimation, Inductance m switching characteristics analytical, empirical delay models, gate delays, CMOS Gate transistor sizing, Power dissipation, Sizing routing conductors, Charge sharing, Yield, reliabili­ty, Scaling of MOS Transistor dimensions
CMOS Circuit and Logic design CMOS logic gate design, Basic Physical design of simple logic gates, CMOS logic struc­tures, Clocking strategies, I/O structures, Lowpower design.
Systems design and Design methods Design strategies, CMOS Chip design options, Design methods, Design capture tools, Design verification tools, design economics
CMOS testing, Need for testing, Manufacturing test princi­ples, design strategies for test, chip level test tech­niques, system level test techniques, Layout design for improved testability
CMOS subsystem design datapath operations, Memory elements, Control FSM design, PLA ROM control implementation, Multile­vel logic.
Theory of logical effort: Method of logical effort, calculation of logical effort of gates, asymmetric logic gates, forks of amplifiers, wide structures.

REFERENCE BOOKS
Jan M Rabaey, Digital integrated circuits: a design perspective, 2nd edition Pearson Education

Neil Weste, Kamran Eshrghian, Principles of CMOS VLSI design: a systems perspective, 2nd ed., Addison Wesley Publishing company, 1993.
Sung-Mo Kang and Y. Leblebici, CMOS digital Integrated Circuits.
Ivan Sutherland. Logical effort, Morgan Kaufeman, CA.